IBM (NYSE: IBM) announced the first-ever application of a breakthrough self-assembling nanotechnology to conventional chip manufacturing, borrowing a process from nature to build the next generation computer chips. The natural pattern-creating process that forms seashells, snowflakes, and enamel on teeth has been harnessed by IBM to form trillions of holes to create insulating vacuums around the miles of nano-scale wires packed next to each other inside each computer chip. In chips running in IBM labs using the technique, the researchers have proven that the electrical signals on the chips can flow 35 percent faster, or the chips can consume 15 percent less energy compared to the most advanced chips using conventional techniques. The IBM patented self-assembly process moves a nanotechnology manufacturing method that had shown promise in laboratories into a commercial manufacturing environment for the first time, providing the equivalent of two generations of Moore's Law wiring performance improvementsin a single step, using conventional manufacturing techniques. This new form of insulation, commonly referred to as “airgaps” by scientists, is a misnomer, as the gaps are actually a vacuum, absent of air. The technique deployed by IBM causes a vacuum to form between the copper wires on a computer chip, allowing electrical signals to flow faster, while consuming less electrical power. The self-assembly process enables the nano-scale patterning required to form the gaps; this patterning is considerably smaller than current lithographic techniques can achieve. A vacuum is believed to be the ultimate insulator for what is known as wiring capacitance, which occurs when two conductors, in this case adjacent wires on a chip, sap or siphon electrical energy from one another, generating undesirable heat and slowing the speed at which data can move through a chip. Until now, chip designers often were forced to fight capacitance issues by pushing ever more power through chips creating, in the process, a range of other problems. They have also used insulators with better insulating capability, but these insulators have become tenuously fragile as chip features get smaller and smaller, and their insulating properties do not compare to those of a vacuum. The self-assembly process already has been integrated with IBM's state-of-the-art manufacturing line in East Fishkill, New York and is expected to be fully incorporated in IBM’s manufacturing lines and used in chips in 2009. The chips will be used in IBM's server product lines and thereafter for chips IBM builds for other companies. "This is the first time anyone has proven the ability to synthesize mass quantities of these self-assembled polymers and integrate them into an existing manufacturing process with great yield results," said Dan Edelstein, IBM Fellow and chief scientist of the self-assembly airgap project. "By moving self assembly from the lab to the fab, we are able to make chips that are smaller, faster and consume less power than existing materials and design architectures allow." Edelstein led the IBM team that invented the technique to use copper wiring in computer chips instead of aluminum, now a standard method for producing chips, ushering in a decade of chip innovations from the IBM labs that transformed how chips were built and used across many industries and applications. The Secret of Self Assembly The secret of IBM's breakthrough lies in how the IBM scientists’ moved the self-assembly process from the laboratory to a production manufacturing environment in a way that can potentially yield millions of chips with consistent, high performance results. Today, chips are manufactured with copper wiring surrounded by an insulator, which involves using a mask to create circuit patterns by beaming light through the mask and later chemically removing the parts that are not needed. The new technique to make airgaps by self-assembly skips the masking and light-etching process. Instead IBM scientists discovered the right mix of compounds, which they pour onto a silicon wafer with the wired chip patterns, then bake it. This patented process provides the right environment for the compounds to assemble in a directed manner, creating trillions of uniform, nano-scale holes across an entire 300 millimeter wafer. These holes are just 20 nanometers in diameter, up to five times smaller than would be possible using today’s most advanced lithography technique. Once the holes are formed, the carbon silicate glass is removed, creating a vacuum between the wires -- known as the airgap -- allowing the electrical signals to either flow 35 percent faster, or to consume 15 percent less energy. Self assembly is a concept scientists have been studying at IBM and in labs around the world as a potential technique to create materials useful for building computer chips. The concept occurs in nature every day, it is how enamel is formed on our teeth, the process that creates seashells and is what transforms water into complex snowflakes. The major difference is, while the processes that occur in nature are all unique, IBM has been able to direct the self-assembly process to form trillions of holes that are all similar. This new technology can be incorporated into any standard CMOS manufacturing line, without disruption or new tooling. The self assembly process was jointly invented between IBM’s Almaden Research Center in San Jose, California and the T.J. Watson Research Center in Yorktown, New York. The technique was perfected for future commercial productionat the College of Nanoscale Science and Engineering of the University at Albany, within the world-class Albany NanoTech facilities, a research and development site in Albany, New York with strong ties to IBM, and at IBM's Semiconductor Research and Development Center in East Fishkill, N.Y. 10 IBM Breakthroughs in 10 Years 10 IBM Breakthroughs in 10 Years -- Beginning with the use of copper for chip wiring, IBM has announced 10 semiconductor innovations over the course of 10 years that have enabled computers and many other kinds of electronic devices to become smaller, less expensive, more powerful, and more energy efficient. IBM today announced it has harnessed the natural tendency of materials to form patterns to create a vacuum between the miles of wires inside chips. This provides better insulation speeding performance and reducing power consumption.

world's first 40G silicon laser modulator!

Announcing the world's first 40G silicon laser modulator!

In this blog, I would like to share with you our recent breakthrough in Silicon Photonics research at Photonics Technology Lab of Intel, a laser modulator that encodes optical data at 40 billion bits per second. Here I am holding a packaged device:

[click here for more pics of the modulator and the research team]

As you may know, a photonic integrated circuit (PIC) could provide a cost-effective solution for optical communication and future optical interconnects in computing industry. PICs on silicon platforms have attracted particular interest because of silicon’s low cost and high volume manufacturability. Competition in this arena is intense as many players in both academia and industry have been aggressively pursuing research into completely integrated CMOS photonics. The DARPA-initiated Electronic & Photonic Integrated Circuits (EPIC) program has also been supporting several Universities and startups to develop capabilities in this area.

One of the key components needed for silicon PICs is the high-speed silicon optical modulator, which is used to encode data on optical beam. Today’s commercially available optical modulators at 10 Gbps are based on more exotic electro-optic materials such as lithium niobate and III-V compound semiconductors. These devices have deployed at speeds up to 40 Gbps. Our goal to achieve similar performance in silicon has been very challenging, because crystalline silicon does not exhibit the linear electro-optic (Pockels) effect used to modulate light in these materials. Engineers are forced to rely on the free-carrier plasma dispersion effect, in which silicon’s refractive index is changed when the density of free carriers (electrons/holes) is varied, to modulate light in silicon.

In 2004, we published in Nature the first silicon modular to reach gigahertz speeds, 50x times faster than previous attempts in silicon. Since then, we scaled the device to 10Gbps, brining silicon modulation speed to a level comparable to most commercial devices. In January 2007, we designed and fabricated a new type of silicon optical modulator scalable to >>10 Gbps and demonstrated data transmission at 30 Gbps (see Optics Express, 22 January 2007, pp. 660-668). The modulator still relies on the free-carrier effect, but its high speed is the result of a unique device design with traveling-wave drive scheme.

This is the new chip on the right. With a similar device configuration, the modulator performance has been further improved by better device packaging to reduce the parasitic effect, better traveling-wave electrode with lower RF attenuation, and better modulator termination circuitry. In the conference of

Integrated Photonics and Nanophotonics Research and Applications, Salt Lake City, Utah, July 9-11, 2007, I presented our world record results in a silicon modulator to a small group of scientists. We have finally reached the goal of data transmission at 40 Gbps speed, matching the fastest devices deployed today using other materials.

The Intel modulator is based on a Mach-Zehnder interferometer with a reverse-biased pn junction in each of the arms (Figure 1a). When a reverse voltage is applied to the junction, free carriers – electrons and holes resulting from the n- and p-dopants – are pulled out of the junction, changing its refractive index via the free-carrier effect. The intensity of the light transmitted through the Mach-Zehnder interferometer is modulated by modulating the phase difference between the interferometer’s two arms. This modulation can be very fast, because free carriers can be swept out of the junction with a time of approximately 7 ps. The modulator speed is thus limited by the parasitic effects such as RC time constant limit.

To minimize the RC constant limitation, Intel researchers adopted a traveling-wave drive scheme allowing electrical and optical signal co-propagation along the waveguide. The traveling-wave electrode which is based on a coplanar waveguide was designed to match the velocity for both optical and electrical signals, while keeping the RF attenuation small. To operate the traveling-wave modulator, the RF signal is fed into the transmission line using a commercially available driver from the optical input side and the transmission line is terminated with an external resistor (see Fig. 1a). After packaging the modulator on a printed circuit board, the researchers demonstrated that the modulator has a 3 dB bandwidth of ~30 GHz (Fig. 2a) and data transmission capability up to 40 Gbps (Fig. 2b).

The high-speed silicon modulator could find use in various future applications. For example, a highly integrated silicon photonic circuit may provide a cost effective solution for the future optical interconnects within computers and other devices. With the demonstration of the 40 Gbps silicon modulator and the electrically pumped hybrid silicon laser, it will become possible to integrate multiple devices on a single chip (Fig. 3) that can transmit terabits of aggregate data per second in the near future – truly enabling tera-scale computing.

Teraflops Research Chip

Advancing Multi-Core Technology into the Tera-scale Era

The Teraflops Research Chip is the latest development from the Intel® Tera-scale Computing Research Program. This chip is Intel's first silicon tera-scale research prototype. It is the first programmable chip to deliver more than one trillion floating point operations per second (1 Teraflops) of performance while consuming very little power. This research project focuses on exploring new, energy-efficient designs for future multi-core chips, as well as approaches to interconnect and core-to-core communications. The research chip implements 80 simple cores, each containing two programmable floating point engines—the most ever to be integrated on a single chip. Floating point engines are used for accurate calculations, such as for graphics as well as financial and scientific modeling. In terms of circuit design, they are more complex than integer engines, which just process instructions.

First row left to right: 80 core teraflops research chip magnified, 80 core teraflops research wafer, Packaged Teraflops Research Chip. Second row left to right: Packaged teraflops research chip on board, Sriram Vangal checking teraflops research chip results, Intel researchers on the Tera-scale Research Project.

Intel's Teraflops Research Chip implements several innovations for multi-core architectures:

• Rapid design - The tiled-design approach allows designers to use smaller cores that can easily be repeated across the chip. A single-core chip of this size (100 million transistors) would take roughly twice as long and twice as many people to design.
• Network on a chip - In addition to the compute element, each core contains a 5-port messaging passing router. These are connected in a 2D mesh network that implement message-passing. This mesh interconnect scheme could prove much more scalable than today's multi-core chip interconnects, allowing for better communications between the cores and delivering more processor performance.
• Fine-grain power management - The individual compute engines and data routers in each core can be activated or put to sleep based on the performance required by the application a person is running. In addition, new circuit techniques give the chip world-class power efficiency—1 teraflops requires only 62W, comparable to desktop processors sold today.
• And other innovations - Such as sleep transistors, mesochronous clocking, and clock gating.

Below is a summary of results from the research chip. Note that while performance gains can still be made through frequency scaling, there is a significant cost in terms of energy efficiency. This underscores the motivation to scale by utilizing more and more cores, instead of just increasing the frequency.

Frequency	Voltage	Power	Aggregate Bandwidth	Performance
3.16 GHz	0.95 V	62W	1.62 Terabits/s	1.01 Teraflops
5.1 GHz	1.2 V	175W	2.61 Terabits/s	1.63 Teraflops
5.7 GHz	1.35 V	265W	2.92 Terabits/s	1.81 Teraflops

ASCI Red was the first computer to benchmark at a teraflops (1996). That system used nearly 10,000 Pentium® Pro processors running at 200MHz and consumed 500kW of power plus an additional 500kW just to cool the room that housed it. Although not a general purpose computing device, this Teraflops Research Chip delivers 1.0 teraflops of performance and 1.6 terabits aggregate core to core communication bandwidth, while dissipating only 62W.

Bringing tera-scale computing to PCs and servers requires a new way of building processors that can be thought of as a network of powerful computers on a chip. This Teraflops Research Chip is one important example of how the Intel® Tera-scale Computing Research Program aims to change the future through constant hardware and software innovation.

Apple Macbook air

Amazingly thin. Amazingly full-size.

The thinness of MacBook Air is stirring. But perhaps more impressive, there’s a full-size notebook encased in the 0.16 to 0.76 inch of sleek, sturdy anodized aluminum. And at just 3.0 pounds,¹ MacBook Air is more than portable — it’s with you everywhere you go.

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A no-compromise display.

The glossy 13.3-inch, widescreen LED backlit MacBook Air display is the same viewable size as the screen on MacBook. The 1280-by-800 resolution gives you vibrant images and rich colors at full brightness the moment you open MacBook Air. So you get full-screen performance with all the benefits of a slim design.

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Full-size, full-feature keyboard.

The keyboard is full-size with crisp keys just like the ones on MacBook. But MacBook Air goes further by adding backlit key illumination, making it easy to work in low-light settings such as airplanes and conference halls. A built-in ambient light sensor automatically adjusts keyboard and display brightness for optimal visibility. And with the oversize multi-touch trackpad, it just keeps getting better for fingers.